`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/07 23:16:25
// Design Name: 
// Module Name: test_tb_w
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_tb_w(

    );
logic ACLK;
logic ARESETn;
logic AWVALID;
logic [31:0] AWADDR;
logic [1:0] AWBURST;
logic [2:0] AWSIZE;
logic [7:0] AWLEN;
logic AWREADY;
logic WVALID;
logic [31:0] WDATA;
logic WLAST;
logic WREADY;
logic [3:0] WSTRB;
logic BVALID;
logic BREADY;
logic [1:0] BRESP;
logic ARVALID;
logic ARREADY;
logic [31:0] ARADDR;
logic [7:0] ARLEN;
logic [31:0] RDATA;
logic RVALID;
logic RLAST;
logic RREADY;
logic [1:0] RRESP;
//
assign ARVALID=0;
initial
begin
    ACLK=0;
	forever
	   #5 ACLK=~ACLK;
end
initial
begin
    ARESETn=0;
	#50
	ARESETn=1;
end
//
//
axi_slave S(.*
/*
input logic ACLK,
input logic ARESETn,
//AR
input logic ARVALID,
input logic [31:0] ARADDR,
input logic [7:0] ARLEN,
output logic ARREADY,
//R
output logic [31:0] RDATA,
output logic RVALID,
output logic RLAST,
output logic [1:0] RRESP,
input logic RREADY,
//AW
input logic AWVALID,
input logic [31:0] AWADDR,
input logic AWLEN,
input logic [2:0] AWSIZE,
input logic [1:0] AWBURST,
output logic AWREADY,
//W
input logic [31:0] WDATA,
input logic WVALID,
input logic WLAST,
input logic [3:0] WSTRB,
output logic WREADY,
//B
output logic BVALID,
output logic [1:0] BRESP,
input logic BREADY
*/
    );
	
axi_master_w M(.*
/*
input logic ACLK,
input logic ARESETn,
//AW
output logic AWVALID,
output logic [31:0] AWADDR,
output logic [7:0] AWLEN,
output logic [2:0] AWSIZE,
output logic [1:0] AWBURST,
input logic AWREADY,
//W
output logic WVALID,
output logic [31:0] WDATA,
output logic WLAST,
output logic [3:0] WSTRB,
input logic WREADY,
//B
input logic BVALID,
input logic [1:0] BRESP,
output logic BREADY
*/
    );
endmodule
